The present invention is an improvement to a CMOS full-adder stage having the features of the preamble of claim l. In particular, the present invention is an improvement to a CMOS full-adder stage such as is disclosed in the published European Patent Application EP-A-No. 112 946, particularly FIG. 5.
During the use of the prior art full-adder stage and the variant according to FIG. 6 of EP-A-No. 112 946 in monolithic integrated parallel adders, it turned out that the maximum possible processing speed is limited by the fact that in each stage, the carry input signal is also applied to transistors which contribute to the summation, so that the carry-signal path is also capacitively loaded.